Guide for Crafting Broad Bandwidth, High-Speed PLL Frequency Synthesizers (First Installment)
In the realm of modern wireless communications, there is a growing demand for high-performance frequency sources, particularly local oscillators (LOs), which must operate at higher frequencies, deliver lower phase noise, and exhibit fast tuning speeds. A recent paper presents a design philosophy for creating very wide loop bandwidth (BW), high-performance PLL frequency synthesizers with a focus on a single-loop Type 2 - 2 Order system featuring a first-order active proportional-integral (PI) loop filter and a dual-path technique.
The technique involves using a Type 2 - 2 Order PLL topology, which features two poles and two zeros, with an active PI loop filter that strategically places a zero for phase margin and stability. The loop filter is first order and provides the essential proportional-integral action to reduce steady-state phase error and speed up settling. The active PI filter ensures precise control of loop dynamics, improving stability and noise shaping.
To extend the effective loop bandwidth, the dual-path loop filter technique is applied. By splitting the loop filter into two signal paths—one path with a fast response (high bandwidth) and the other with a slower response (low bandwidth)—a very wide instantaneous loop bandwidth can be achieved without compromising stability or inducing excessive noise. The fast path controls quick phase noise suppression close to the carrier, while the slow path handles longer-term frequency accuracy and noise far from the carrier.
The primary goal of this design approach is to achieve low phase noise and fast settling, which are crucial for high-frequency, fast-tuning applications like millimeter-wave and 5G/6G systems. The dual-path technique enables these wide bandwidths without the usual trade-offs in loop stability or spur generation.
Key design considerations include precisely defining loop filter components for the desired bandwidth and phase margin, optimising the PLL divider and phase detector parameters to complement the loop filter behaviour, considering noise contributions from the VCO, phase detector, and divider, addressing them via loop bandwidth partitioning, using simulation tools to verify loop stability and noise performance, and fine-tuning the PI parameters and dual-path constants.
This design philosophy is detailed in contemporary sources emphasising challenges in very high-frequency PLL synthesis for demanding communications like 5G/6G and mmWave, highlighting the balance between loop bandwidth, stability, and low phase noise through specialized loop filter topologies and dual-path filtering to achieve top-tier performance.
The paper, which is part 1 of a series, discusses a special technique for producing wide loop BWs in high-frequency PLL synthesizers, aiming for low phase noise comparable to that of direct synthesizers. The paper is a compilation of work by top technical professionals in frequency synthesizers, radio/radar, and communications systems. An example single-loop PLL synthesizer used as a high-side 1 LO in a high-performance superheterodyne receiver is presented, with the priority interest being in producing the lowest possible phase noise.
Given the high frequency and high performance of the synthesizer, the components used are all discrete and of the packaged surface-mount variety. The paper specifically highlights the work done by a staff scientist and subject-matter expert who initiated the synthesizer concept and original design, and produced a prototype unit. The author of the paper collaborated with these professionals, exchanging ideas, and taking leadership of the synthesizer project with his own team.
The paper references several books and resources related to PLLs, frequency synthesizers, and related topics. If you need formal design equations or simulations, literature on Type 2 PCM PLLs with active PI filters and dual-path techniques would be the next step.
[1] Reference omitted for brevity.
Technology plays a crucial role in the design of high-performance PLL frequency synthesizers, particularly those demanded in modern wireless communications like 5G/6G and millimeter-wave systems. Thepaper presents a special technique for producing wide loop bandwidths in these synthesizers, aiming for low phase noise comparable to that of direct synthesizers, utilizing a Type 2 - 2 Order PLL topology, first-order active proportional-integral (PI) loop filter, and dual-path filtering.
){kind=link}